(1) Field of the Invention
The invention relates to a machine and method for vacuum degassing, controlled ramping to the curing temperature, and curing of a spin-on-glass (SOG) planarization layer for an integrated circuit device.
(2) Description of the Prior Art
The growing and regrowing of insulating films such as silicon dioxide and the use of polysilicon and/or metals in the form of conductors, ohmic contacts, resistors and the like in the manufacture of integrated circuits cause irregular or substantially non-planar surfaces across the surface of the semiconductor substrate. A major problem that is caused by these irregular or non-planar surfaces is loss of resolution in the lithographic masking processed. For example, metal conductors formed on the insulating films have different widths across the surface of the semiconductor body due to the different resist development because of the resolution problems. To prevent conductors from having varying widths to the point where they might cause short circuits, extra spacing or tolerances are required with each conductor. The increased tolerances reduce the number of devices that may be formed in the semiconductor structure. This problem increases with each higher level of metallurgy and with the use of submicron lithography features. In these highly dense, submicron integrated circuits 3 or 4 levels of interconnection metallurgy is required.
These problems have been recognized in the prior art and attempts have been made to overcome these topographical problems principally in the one micron and above feature dimensions. These techniques can be generally grouped in categories of planarization either involving etchback or nonetchback techniques. Examples of such processes are shown in the S. Morimoto U.S. Pat. No. 4,721,548; W. I. Lehrer U.S. Pat. No. 4,619,839; J. K. Chu et al U.S. Pat. No. 4,775,550; V. W. Ryan et al U.S. Pat. No. 4,826,709 and C. T. Ting et al U.S. Pat. No. 4,885,262.
The coupling patent applications Ser. No. 07/512,401 entilted "Semiconductor Planarization Process for Submicron Devices" and Ser. No. 07/615377 entitled "Planarization Process for IC Submicron Devices" by Daniel L. W. Yen the same author of the present invention describe methods to overcome the problems involving outgassing in the nonetchback type of planarization process for both silicate and siloxane type of spin-on-glass types of materials. These new inventions have made it necessary to design and develop a new machine and method for high vacuum, controlled ramping curing furnace which allows successful vacuum degassing and curing of a spin-on-glass layer within the same machine.
It is therefore a primary object of this invention to provide a machine and method for a high vacuum, controlled ramping vacuum degassing and curing of a spin-on-glass layer to complete the planarization of an integrated circuit device.